The present disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices, and more particularly, to semiconductor devices including a metal-insulator-semiconductor field-effect transistor (MISFET) having source/drain regions including a silicon compound layer, and methods for fabricating the semiconductor devices.
A technique of enhancing the drive capability of a MISFET (hereinafter referred to as a “MIS transistor”) by applying a stress to the channel region of the MIS transistor has been employed so as to improve the performance of a semiconductor integrated circuit device. For p-type MIS transistors, it is known that if a compressive stress is applied to the channel region in the gate length direction, the mobility of carriers is increased, whereby the drive capability of the p-type MIS transistor is enhanced. For example, a compressive stress may be applied to the channel region in the gate length direction by forming, in the source/drain regions, a SiGe layer having a larger lattice constant than that of the silicon substrate (see, for example, PATENT DOCUMENT 1: Japanese Patent Publication No. 2006-196549, NON-PATENT DOCUMENT 1: T. Ghani et al., “A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors,” IEDM Tech. Digest, pp. 978-980, 2003, and NON-PATENT DOCUMENT 2: Z. Luo et al., “Design of High Performance PFETs with Strained Si Channel and Laser Anneal,” IEDM Tech. Digest, pp. 495-498, 2005).
A method for fabricating a conventional semiconductor device including a p-type MIS transistor having p-type source/drain regions including a SiGe layer and an n-type MIS transistor will be described hereinafter with reference to FIGS. 8A-8C, 9A-9C, and 10A-10C. FIGS. 8A-10C are cross-sectional views showing the conventional semiconductor device as viewed in the gate length direction, in the order in which the semiconductor device is fabricated. In FIGS. 8A-10C, the term “pMIS region” shown on the left side refers to a region where the p-type MIS transistor is formed, and the term “nMIS region” shown on the right side refers to a region where the n-type MIS transistor is formed.
Initially, as shown in FIG. 8A, an isolation region 101 is selectively formed in an upper portion of a semiconductor substrate 100. As a result, a first active region 100a surrounded by the isolation region 101 is formed in the pMIS region of the semiconductor substrate 100. A second active region 100b surrounded by the isolation region 101 is formed in the nMIS region of the semiconductor substrate 100. Thereafter, an n-type well region 102a is formed in the pMIS region of the semiconductor substrate 100. On the other hand, a p-type well region 102b is formed in the nMIS region of the semiconductor substrate 100.
Next, on the first and second active regions 100a and 100b, a first and a second gate electrode formation portion 105A and 105B are formed which include a first and a second gate insulating film 103a and 103b, a first and a second gate electrode 104a and 104b, and a first and a second protective insulating film 105a and 105b made of a silicon oxide film.
Next, first and second offset spacers 106a and 106b made of a silicon oxide film are formed on side surfaces of the first and second gate electrode formation portions 105A and 105B. Thereafter, p-type and n-type extension injection regions 107a and 107b are formed in the first and second active regions 100a and 100b laterally outside the first and second gate electrode formation portions 105A and 105B (i.e., are formed in the first and second active regions 100a and 100b adjacent to the channel region and extending laterally away from it).
Next, as shown in FIG. 8B, first and second sidewalls 109A and 109B including first and second inner sidewalls 108a and 108b made of a silicon oxide film, and first and second outer sidewalls 109a and 109b made of a silicon nitride film, are formed on side surfaces of the first and second gate electrode formation portions 105A and 105B, with the first and second offset spacers 106a and 106b being interposed between the first and second inner sidewalls 108a and 108b and the side surfaces of the first and second gate electrode formation portions 105A and 105B.
Next, as shown in FIG. 8C, an insulating film 110 made of a silicon oxide film is formed on an entire surface of the semiconductor substrate 100.
Next, as shown in FIG. 9A, a resist pattern (not shown) which exposes the pMIS region and covers the nMIS region is formed on the insulating film 110 by a lithography process. Thereafter, the insulating film 110 is etched by dry etching using the resist pattern as a mask. As a result, a surface of the first active region 100a is exposed. On the other hand, the insulating film 110 which covers the second gate electrode formation portion 105B and the first sidewalls 109B is left on the second active region 100b. In this case, unnecessary sidewalls 110a are left on side surfaces of the first sidewalls 109A. Thereafter, the resist pattern is removed.
Next, as shown in FIG. 9B, the first active region 100a is etched using the sidewalls 110a and the insulating film 110 as a mask. As a result, trenches 111 are formed in the first active region 100a laterally outside the sidewalls 110a. 
Next, as shown in FIG. 9C, a SiGe layer 112 doped with a p-type impurity is formed in the trenches 111. Because the SiGe layer 112 is doped with the p-type impurity, the regions of the SiGe layer 112 are p-type impurity-introduced regions.
Next, as shown in FIG. 10A, the first and second protective insulating films 105a and 105b (silicon oxide film), the sidewalls 110a (silicon oxide film), and the insulating film 110 (silicon oxide film) are removed. As a result, upper surfaces of the first and second gate electrodes 104a and 104b, and the first and second sidewalls 109A and 109B, are exposed.
Next, as shown in FIG. 10B, n-type source/drain implanted regions 113 are formed in the second active region 100b laterally outside the second sidewalls 109B.
Next, as shown in FIG. 10C, a thermal treatment is performed. As a result, the p-type impurity contained in the p-type extension injection regions 107a is activated to form p-type extension regions 114a. The n-type impurity contained in the n-type extension injection regions 107b is activated to form n-type extension regions 114b. The p-type impurity contained in the regions (p-type impurity-introduced regions) of the SiGe layer 112 is activated to form p-type source/drain regions 115a. The n-type impurity contained in the n-type source/drain implanted regions 113 is activated to form n-type source/drain regions 115b. 
Thereafter, although not shown, a first and a second silicide layer are formed on the first and second gate electrodes 104a and 104b, and a third and a fourth silicide layer are formed on the p-type and n-type source/drain regions 115a and 115b. 
Thus, the conventional semiconductor device is fabricated.